Driving method, driving circuit and driving apparatus for a display system

ABSTRACT

A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.

The invention relates to a method of operating a driving circuit for adisplay system, wherein a sequence of writing and/or reading video datain to and/or from a memory is controlled by means of an addresssequencer, each of the memory addresses for said video data generated inthe address sequencer being composed of a picture line address part orline pointer and an address part for a pixel on said picture line.

This method is applied in display systems such as Cathode Ray Tubes(CRT), Plasma Discharge Panels (PDP), Liquid Crystal Displays (LCD), andone-panel Liquid Crystal on Silicon (LCOS). All of them requiredifferent addressing sequences. Frame memories are widely used asdriving circuits for these display systems. External or embedded staticor dynamic random access memories (SRAM's or DRAM's) are often used asframe memories for re-ordering video information. Sequencers normallycontrol the order of reading and writing. If the driving circuit issupposed to work with different resolutions, e.g. zooming orsplit-screen monitoring, or is to be able to drive different kinds ofthe above-mentioned displays, a flexible addressing of the frame memoryis needed for re-ordering pixel data. In particular, the driving circuitmust be flexible enough to generate sequences such as interlacedsequences and color sequential sequences, and flexible enough to handledesign changes, for example in the optical layout of the LCOS system.

A possible solution may be found in the design of the sequencer in theform of a number of counters combined with logic. However, thedifficulty thereof is that this is basically a non-flexible solution.The different sequences to be produced have to be known in advance toguarantee a coverage of all required solutions.

Another possible solution may be a sequence table approach, wherein thewhole sequence is stored into a random access memory that is part of thesequencer. This solution offers all the required flexibility inprinciple. Such a solution is known from U.S. Pat. No. 5,587,962. Thispatent specification discloses a device with a frame memory circuitwhich permits limited random access and is used to perform a widevariety of special-effect video applications. The frame memory circuitof this device stores and provides streams of data and supports bothserial access and random access. A data input of a random access memoryarray couples to a data buffer, so that the data buffer may synchronizeoperation of the memory array with the streams of data. An address inputof the random access memory array couples to one address sequencer,which generates a sequence of memory addresses that are successivelyapplied to the memory array. An address buffer register also couples tothe address sequencer. U.S. Pat. No. 5,587,962 provides a memory circuitwhich serves as a frame memory and permits special effects like zoom orsplit-screen and other effects to be performed efficiently. For that,the memory circuit represents a single-chip integrated circuit thatcontains 2²⁰ bits of memory storage organized as 262,144 four bit widewords with special write and read access arrangements. The memorycircuit generally operates in a serial access mode for both write andread operations, but has particular features which permit random accessfor writing or reading of the memory circuit on a limited scale. Forreceiving analog video signals converted to digital pixels, the memorycircuit includes a serial pixel data input, which supplies four bits ofdata per pixel. The serial pixel data input couples to an input port ofa write serial latch, and an output port of the write serial latchcouples to an input port of a write register. An output port of thewrite register couples to a data input port of a memory array. Thememory array is a dynamic random access memory array containing 2¹⁸ fourbit memory locations. A data output port of the memory array couples toa data input port of a read register, and a data output port of a readregister couples to a data input port of a read serial latch. Thearbitration and control circuit passes an address generated by theaddress generator to the memory array so that the data may be writteninto the memory array, but a delay may occur due to refresh operationsor read accesses to the memory array. Accordingly, the arbitration andcontrol circuit may additionally contain storage devices so thataddresses generated by address generators are not lost when immediateaccess to the memory array is blocked. U.S. Pat. No. 5,587,962 disclosesa table-based solution. The solution is table-based because the wholesequence is stored on a DRAM memory array that is part of the framememory circuit. As was noted above, the solution offers all the requiredflexibility in principle. However, this solution has the disadvantagethat the size of the table must be relatively large. For example, anUXGA-based LCOS design has 1200 lines, so the table has to have 1200entries of, in practice, 21 bit each, resulting in a table of about 25kbits.

The object of the invention is provide a method of operating a drivingcircuit with a sequencer as described in the opening paragraph which hasthe flexibility of the above table-based sequencer but is lessexpensive.

Therefore, according to the invention, this method is characterized inthat switching means operate the driving circuit alternately in a firstmode wherein the address sequencer generates addresses for the videodata in the memory by combining line pointers from a block of linepointers in address table register means with the output of pixelcounting means and in a second mode wherein a block of line pointersfrom a full table of line pointers in said memory is downloaded intosaid address table register means.

As already mentioned, the invention further relates to a driving circuitfor a display system wherein the method according to the invention isapplied. This driving circuit comprises a memory for video data to bedisplayed and coupled thereto an address sequencer for controlling thesequence of writing and/or reading the video data in said memory, and ischaracterized in that the memory contains a full table of line pointers,each line pointer being part of a memory address for video data, and inthat the address sequencer is provided with address table register meansfor a block of line pointers from said table of line pointers, means forsuccessively updating the address table register means with subsequentblocks of line pointers, and pixel counting means, the output of whichin combination with the consecutive line pointers from the address tableregister means determines the addresses for said video dataParticularly, switching means are provided by which alternately memoryaddresses for video data are generated in a first mode in the addresssequencer, and in a second mode the address table register is updatedwith a next block of line pointers. In a practical embodiment, the fulltable of line pointers for different sequences of video data to bedisplayed will be incorporated in the memory.

The invention also relates to an apparatus for displaying imagescomprising a display system and a driving circuit as described above.

The invention further relates to an algorithm for processing addressesin said driving circuit and said apparatus. The invention also relatesto a computer program capable of running on signal processing means insaid driving circuit, and to an information carrier containing saidcomputer program.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiment described hereinafter,wherein

FIG. 1 shows the system setup of a driving circuit for a displayaccording to the invention in normal operation;

FIG. 2 shows the system setup of the driving circuit for addresstransfer;

FIG. 3 shows a flow diagram for the method used during normal operation;

FIG. 4 shows a flow diagram for the method used during reading of atable block from the main memory into the address table register;

FIG. 5 shows a flow diagram for the method used, illustrating therepeatedly executed address table block transfer; and

FIG. 6 shows an apparatus provided with a driving circuit according tothe invention.

FIG. 1 shows the system setup of a driving circuit for a display innormal operation, comprising a main memory 1 and an address sequencer 2.The main memory 1 includes a frame memory 3. Video data is stored in theframe memory 3 in a first sequence and read out therefrom in a secondsequence. The frame memory addresses, therefore, are generated by theaddress sequencer 2. In the present embodiment, the video data is formedby progressive video signals with one component, the luminance (Y)component, which signals for the sake of simplicity are supposed to bewritten sequentially and read out in an interlaced or color-sequentialmanner. Alternatively, an interlaced signal could be converted into aprogressive signal by applying the present invention.

The address sequencer 2 is provided with an address table register 4containing a table of line pointers. These line pointers form part ofthe frame memory addresses, indicating line addresses. During normaloperation, consecutive line pointers are read out from the address tableregister 4 by a line counter 5 and supplied to a first input of an adder6. A pixel counter 7 is coupled to the second input of the adder 6. Theconsecutive output signals of the adder 6 represent the frame memoryaddresses for the frame memory 3. The consecutive frame memory addressesdetermine the sequence in which video signals stored in the frame memory3 are read out therefrom or the sequence in which video signals suppliedto the frame memory 3 are stored therein.

If, for example, the system is used in combination with a display having480 lines, the line counter 5 runs from 0 to 479; if one line contains720 pixels, the pixel counter 7 runs from 0 to 719. If the address tableregister 4 contains 480 line addresses of usually 21 bits, a table ofabout 10 kbit will be necessary, which is relatively expensive. With adisplay of 1200 lines and an address table register 4 containing 1200line addresses of 21 bits, a table of about 25 kbits will be necessary.According to the invention, the number of line pointers in the addresstable register 4 is limited, for example to 32; this results in anaddress table of about 0.7 kbit. So, the address table register 4 canonly contain blocks of line pointers. This, however, requires a constantupdating of the address table register 4; for reading out a frame of 480lines the address table register 4 must be updated 15 times. To makethis possible, all line pointers are stored in the main memory 1. Eachtime a block of line pointers is successively read out from the addresstable register 4, a next block of line pointers is transferred from themain memory 1 into the address table register 4. This process, thesystem setup for (line) address transfer, will be clarified withreference to FIG. 2. Both the system setup in normal operation and thesystem set up for address transfer occur under the control of a controlprocessor 8 which forms part of the address sequencer 2.

FIG. 2 shows the system setup for address transfer. When the last linepointer of a block of lines pointers in the address table register 4 isread out, the address sequencer 2 reads a new block of line pointersfrom the main memory 1, i.e. a next block of line pointers is downloadedinto the address table register 4. This requires a base address register9, containing the base address or start address for a block of linepointers in the main memory 1, and an address counter 10. An adder 11forms the addresses for the line pointers in the main memory 1 andsupplies them thereto in the read mode (read=1 in FIG. 2) of the framememory 3. These addresses represent an index for the line pointers inthe frame memory 3. This index is as large as the number of lines of thedisplay. In the write mode (read=0), the addressed line pointers aretransferred to the address table register 4. So, the whole system isconstantly switching between the table update mode and the addresssequence mode (the normal mode).

FIG. 3 shows the flow diagram for the method used during normaloperation. During initialization the line counter 5 is reset to i=0. Thenext step is the generation of the consecutive frame memory or pixeladdresses (k=0 . . . . N-1, wherein N is the number of pixels of a line)for a first line and the video data transfer realized by means of theseaddresses. Thereafter the line counter 6 is increased by 1 (i:=i+1) andthe frame memory or pixel addresses for the next line are generated,realizing a corresponding video data transfer. This process continuesuntil the frame memory or pixel addresses for the last line have beengenerated. When the last line is reached, the loop has finished.

FIG. 4 shows the reading of a block of line pointers from the mainmemory 1 into the address table register 4. During initialization, thebase address in the base address register 9 for a block of line pointersis reset to j=0. Then, during (line) address transfer, the line pointercorresponding to base address j=0 is read from the frame memory 1 intothe address table register 4. Thereafter, the base address issuccessively increased by 1 (j:=j+1), and the corresponding linepointers are read from the main memory 1 into the address table register4. This loop continues until the last line pointer of the block of linepointers has been downloaded into the address table register 4.

FIG. 5 shows the flow diagram for the method used, illustrating therepeatedly executed address table block transfer. During initialization,the block of line pointers in the address table register 4 is moved intothe main memory 1, and the line counter 5 is reset to i=0. Then the loopfor video data transfer starts. First block 1 is read from the mainmemory 1 into the address table register 4. Then video datacorresponding to block 1 is transferred to the display. Thereafter,successively, next blocks of line pointers are downloaded, and the videodata corresponding to these blocks are transferred. After the last blockof line pointers has been downloaded and the corresponding video datahas been transferred, the loop is finished.

FIG. 6 shows an apparatus 100 for displaying images, comprising thedriving circuit according to the invention. The apparatus 100 comprisesa display 101, a main memory 1 with a frame memory 3, and an addresssequencer 2. For example, the display 101 is chosen from the groupconsisting of CRT, PDP, and one-panel LCOS. The address sequencer 2 andthe frame memory 3 are coupled for bidirectional data transfer, forexample using a standard interface 102. The main memory 1 is alsocoupled to the display 101 for the transfer of video data.

The invention is not restricted to the preferred embodiment shown in theFigures. Modifications are possible. As was stated above, the addresssequencer is composed of a picture line address part or line pointer andan address part for the pixels on a picture line. In the embodimentdescribed, the line pointer relates to a full address line and the pixeladdress part to all the pixels of a picture line. However, it may alsobe possible that the line pointer relates to part of a picture line, forexample half a picture line; in that case the pixel address part relatesonly to the pixels of half a picture line, too. Also, the line pointermay relate to more than one, for example two picture lines; in that casethe pixel address part relates to the pixels of two picture lines.

1. Method of operating a driving circuit for a display system, whereinthe sequence of writing and/or reading video data into and/or from amemory is controlled by means of an address sequencer, each of thememory addresses for said video data generated in the address sequencerbeing composed of a picture line address part or line pointer and anaddress part for a pixel on said picture line, characterized in thatswitching means operate the driving circuit alternately in a first modewherein the address sequencer generates addresses for the video data inthe memory by combining line pointers from a block of line pointers inaddress table register means with the output of pixel counting means,and in a second mode wherein a block of line pointers from a full tableof line pointers in said memory is downloaded into said address tableregister means.
 2. Driving circuit for a display system comprising amemory for video data to be displayed and coupled thereto an addresssequencer for controlling the sequence of writing and/or reading thevideo data in said memory, characterized in that the memory contains afull table of line pointers, each line pointer being part of a memoryaddress for video data, and in that the address sequencer is providedwith address table register means for a block of line pointers from saidtable of line pointers, means for successively updating the addresstable register means with subsequent blocks of line pointers, and pixelcounting means, the output of which in combination with the consecutiveline pointers from the address table register means determines theaddresses for said video data.
 3. Driving circuit as claimed in claim 2,characterized in that switching means are provided by which alternatelymemory addresses for video data are generated in a first mode in theaddress sequencer, and in a second mode the address table register isupdated with a next block of line pointers.
 4. Driving circuit asclaimed in claim 2, characterized in that the memory comprises a fulltable of line pointers for different sequences of video data to bedisplayed.
 5. Apparatus for displaying images comprising a displaysystem and a driving circuit according to any one of the claim
 2. 6.Algorithm for processing addresses in a driving circuit for a displaysystem according to any one of the claim 2 and in the apparatusaccording to claim
 5. 7. Computer program capable of running on signalprocessing means in a driving circuit for a display system according toany one of the claim 2 or in the apparatus according to claim
 5. 8.Information carrier containing the computer program according to claim7.